The present invention relates to a memory cell for data storage applications, and more particularly, to embodiments of a memory cell including a magnetic tunnel junction (MTJ) memory element coupled to a two-terminal selector device in series.
Spin transfer torque magnetic random access memory (STT-MRAM) is a new class of non-volatile memory, which can retain the stored information when powered off. A conventional STT-MRAM device normally comprises an array of memory cells, each of which includes a magnetic memory element and a selection transistor coupled in series between appropriate electrodes. The selection transistor functions like a switch to direct current or voltage through the selected magnetic memory element coupled thereto. Upon application of a switching current through the magnetic memory element, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
FIG. 1 is a schematic circuit diagram of a conventional magnetic memory array 20, which comprises a plurality of memory cells 22 with each of the memory cells 22 including a selection transistor 24 coupled to a magnetic memory element 26; a plurality of parallel word lines 27 with each being coupled to the gates of a respective row of the selection transistors 24 in a first direction; a plurality of parallel bit lines 28 with each being coupled to a respective row of the magnetic memory elements 26 in a second direction substantially perpendicular to the first direction; and a plurality of parallel source lines 29 with each being coupled to a respective row of the selection transistors 24 in the second direction.
The use of the two-terminal selector instead of transistor would allow the memory cell to attain the minimum cell size of 4 F2, where F denotes the minimum feature size or one half the minimum pitch normally associated with a particular manufacturing process, thereby increasing memory array density. However, conventional bidirectional two-terminal selector devices, such as Ovonic threshold switch (OTS), have relatively low on/off ratio and are prone to current leakage compared with conventional selection transistors.
For the foregoing reasons, there is a need for a bidirectional two-terminal selector device for memory applications that has high on/off switching speed and low current leakage and that can be inexpensively manufactured.